Sunday October 3, 2010
17.00-18.00		CONFERENCE REGISTRATION
18.00-19.00		ICCD 2010 RECEPTION
		Monday October 4, 2010
08.00-08.30		WELCOME COFFEE
08.30-09.00		CONFERENCE REGISTRATION
09.00-09.15		WELCOME by Georgi Gaydadjiev and Peter-Micheal Seidel
09.15-10.15		KEYNOTE PRESENTATION 1
		Wolfgang Paul
		Computational Models for the Age of Multicore Processing
10.15-10.45		COFFEE BREAK
10.45-12.05		Session 1.1 Architecture Innovation for High Performance Session Chair: Jarmo Takala, Tampere Univ. of Technology, Finland			Session 1.2 Synchronous Circuits and Interfaces Session Chair: Vassos Soteriou, Cyprus University of Technology, Cyprus			Session 1.3 Simulation, Optimization and Scheduling Session Chair: Andy Pimentel, University of Amsterdam, NL
	PAPER ID	ROOM 1		PAPER ID	ROOM 2		PAPER ID	ROOM 3
10.45	192	Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro Lopez and David Kaeli	10.45	232	Jean-Michel Chabloz and Ahmed Hemani	10.45	288	Bin Xue and Sandeep Shukla
	REG	Out-of-Order Retirement of Instructions in Sequentially Consistent Multiprocessors		REG	Lowering the Latency of Interfaces for Rationally-Related Frequencies		REG	Optimization Back Pressure and Throughput for Latency Insensive System
11.10	266	Daniel Kopta, Josef Spjut, Erik Brunvand and Al Davis	11.10	23	Rick Nas and Kees van Berkel	11.10	128	Yue Qian, Zhonghai Lu and Qiang Dou
	REG	Efficient MIMD Architectures for High-Performance Ray Tracing		REG	High Throughput, Low Set-up Time, Reconfigurable Linear Feedback Shift Register		REG	QoS Scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin
11.35	176	Anup Das, Rance Rodrigues, Israel Koren and Sandip Kundu	11.35	114	Rami Abdallah and Naresh Shanbhag	11.35	186	Stefano Frache, Mariagrazia Graziano and Maurizio Zamboni
	REG	A Study on Performance Benefits of Core Morphing in a Asymmetric Multicore Processor		REG	Robust and Energy-Efficient DSP Systems via Output Probability Processing		SHORT	A Flexible Simulation Methodology and Tool for Nanoarray-based Architectures
						11.50	90	Zhuo Ruan, Kurtis Cahill and David Penry
							SHORT	Elaboration-time Synthesis of High-level Language Constructs in SystemC-based Microarchitectural Simulators
12.05-13.30		LUNCH
13.30-15.45		Session 2.1 High Performance Cache Architecture Session Chair: Mohamed Zahran, New York University, USA			Session 2.2 Energy/Area efficient Circuit Design in Conventional and Emerging Technologies Session Chair: Georgi Kuzmanov, TU Delft, The Netherlands			Session 2.3 Real-Time and Embedded Systems Session Chair: Sandip Kundu, University of Massachusetts Amherst, USA
	PAPER ID	ROOM 1		PAPER ID	ROOM 2		PAPER ID	ROOM 3
13.30	2	Rami Sheikh and Mazen Kharbutli	13.30	9	Nam Sung Kim	13.30	6	Linwei Niu
	REG	Improving Cache Performance by Combining Cost-Sensitivity and Locality Principles in Cache Replacement Algorithms		REG	Minimizing Total Area of Low-Voltage SRAM Array with Joint Optimization of Cell Size, Redundancy, and ECC		REG	Rate-Monotonic Scheduling for Reducing System-Wide Energy Consumption for Hard Real-time Systems
13.55	140	Amirali Baniasadi, Ali Shafiee and Narges Shahidi	13.55	72	Morteza Damavandpeyma, Sander Stuijk, Twan Basten, Marc Geilen and Henk Corporaal	13.55	89	Xiaorong Zhang, He Huang and Qing Yang
	REG	HELIA: Heterogeneous Interconnect for Low Resolution Cache Access in Snoop-based Chip Multiprocessors		REG	Thermal-Aware Scratchpad Memory Design and Allocation		REG	Design and Implementation of A Special Purpose Embedded System for Neural Machine Interface
14.20	56	Chuanjun Zhang and Bing Xue	14.20	74	Shruti Patil, Andrew Lyle, Jonathan Harms, David Lilja and Jian-Ping Wang	14.20	32	Ali Sharif Ahmadian, Mahdieh Hosseingholi and Alireza Ejlali
	REG	A Tag-Based Cache Replacement		REG	Spintronic Logic Gates for Spintronic Data Using Magnetic Tunnel Junctions		REG	A Control-Theoretic Energy Management for Fault-Tolerant Hard Real-Time Systems
14.45	164	Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa and Hiroaki Kobayashi	14.45	328	Yehua Su and Wenjing Rao	14.45	80	Matthias Mueller, Joachim Gerlach and Wolfgang Rosenstiel
	SHORT	A Voting-Based Working Set Assessment Scheme for Dynamic Cache Resizing Mechanisms		SHORT	Modeling and Assessing Nanocrossbar Logic Mapping Using Mismatch Number Distribution		REG	RTOS-Aware Modeling of Embedded Hardware/Software Systems
15.00	202	Samira Khan and Daniel Jimenez	15.00	200	Mehrdad Khatir, hassan ghasemzadeh mohammadi and Alireza Ejlali	15.10	267	Paolo Burgio, Martino Ruggiero, Francesco Esposito, Mauro Marinoni, Giorgio Buttazzo and Luca Benini
	REG	Insertion Policy Selection Using Decision Tree Analysis		SHORT	Sub-Threshold Charge Recovery Circuits		REG	Adaptive TDMA bus Allocation and Elastic Scheduling: a unified approach for enhancing robustness in multi-core RT systems
			15.15	279	Weiguo Tang and Lei Wang
				SHORT	Data Rate Maximization by Adaptive Thresholding RF Power Management under Renewable Energy
			15.30	162	Marco Cannizzaro, Weiwei Jiang and Steven Nowick
				SHORT	Practical Completion Detection for 2-of-N Delay-Insensitive Codes
15.45-16.15		COFFEE BREAK
16.15-17.00		KEYNOTE PRESENTATION 2
		Felix Eberli
		Automotive Embedded Driver Assistance: A Real-Time Low-Power FPGA Stereo Engine using Semi-Global Matching
19.00-22.00		GALA DINNER (at the Conference Hotel)
		Tuesday October 5, 2010
08.00-08.30		WELCOME COFFEE
08.30-09.30		KEYNOTE PRESENTATION 3
		David Brash
		Recent additions to the ARMv7-A architecture
09.30-10.00		COFFEE BREAK
10.00-12.10		Session 3.1 Advances in Physical Design and Synthesis Session Chair: Prof. Deming Chen, UIUC, USA			Session 3.2 Circuits for Arithmetic, Cryptography and Signal Processing Session Chair: Hans Vandierendonck, Ghent University, Belgium			Session 3.3 Multiprocessor Systems
	PAPER ID	ROOM 1		PAPER ID	ROOM 2		PAPER ID	ROOM 3
10.00	160	Glauco Santos, Tiago Reimann, Ricardo Reis and Marcelo Johann	10.00	253	Patricio Bulic, Zdenka Babic and Aleksej Avramovic	10.00	216	Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson and Uri C. Weiser
	REG	The Fidelity Property of the Elmore Delay Model in Actual Comparison of Routing Algorithms		REG	A Simple Pipelined Logarithmic Multiplier		REG	Threads vs. Caches: Modeling the Behavior of Parallel Workloads on High-Performance Engines
10.25	101	Zhi-Wei Chen and Jin-Tai Yan	10.25	323	Malte Baesler, Sven-Ole Voigt and Thomas Teufel	10.25	18	Peter Poplavko, Marc Geilen and Twan Basten
	REG	Routability-Driven Flip-Flop Merging Process for Clock Power Reduction		REG	A Radix-10 Digit Recurrence Division Unit with a Constant Digit Selection Function		REG	Predicting the Throughput of Multiprocessor Applications under Dynamic Workload
10.50	275	Vinayak Honkote and Baris Taskin	10.50	87	Somayeh Timarchi, Mahmood Fazlali and Sorin Cotofana	10.50	96	Pengfei Gou, Qingbo Li, Qi Zheng, Yinghan Jin, Bing Yang, Jinxiang Wang and Mingyan Yu
	REG	Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array		REG	Reliable Structure for Moduli Set {2n-1, 2n, 2n+1} Adders Based on a Novel RNS Representation		REG	M5 Based EDGE Architecture Modeling
11.15	161	John Lee and Puneet Gupta	11.15	174	Shohreh Sharif and Elena Dubrova	11.15	94	Michael Baker and Karam S. Chatha
	REG	Incremental Gate Sizing for Late Process Changes		SHORT	Pulse Latch Based FSRs for Low-Overhead Hardware Implementation of Cryptographic Algorithms		REG	A Lightweight Runtime Scheduler for Streaming Multicore Applications
			11.30	185	Vaibhav Gupta, Georgios Karakonstantis, Debabrata Mohapatra and Kaushik Roy
11.40	196	Sanghamitra Roy and Koushik Chakraborty		SHORT	VEDA: Variation-aware Energy-efficient Discrete wavelet transform Architecture	11.40	181	Peter van Stralen and Andy D. Pimentel
	SHORT	Microarchitecture Aware Gate Sizing: A Framework for Circuit-Architecture Co-Optimization					REG	Scenario-Based Design Space Exploration of MPSoCs
			11.45	278	Jason Thong and Nicola Nicolici
11.55	226	Mayler Martins, Leomar Rosa Jr., Anders Rasmussen, Renato Ribas and Andre Inacio Reis		REG	Combined Optimal and Heuristic Approaches for Multiple Constant Multiplication
	SHORT	Boolean Factoring with Multi-Objective Goals
12.10-13.30		LUNCH
13.30-15.35		Session 4 Best Papers
	PAPER ID	ROOM 1
13.30	97	Joonsoo Kim, Jacob A. Abraham and Joonsoo Lee
	REG	Toward Reliable SRAM-based Device Identification
13.55	191	Wei SHi, Zhiying Wang, Hongguang Ren, Ting Cao, wei chen, Bo Su and Hongyi Lu
	REG	DSS: Applying Asynchronous Techniques to Architectures Exploiting ILP at Compile Time
14.20	12	Navid Toosizadeh, Safwat G. Zaky and Jianwen Zhu
	REG	Using Variable Clocking to Reduce Leakage in Synchronous Circuits
14.45	31	Shih-Lun Huang, Chung-Wei Lin and Yao-Wen Chang
	REG	Efficient Provably Good OPC Modeling and Its Applications to Interconnect Optimization
15.10	108	Seokin Hong and Soontae Kim
	REG	Lizard: Energy-efficient Hard Fault Detection, Diagnosis and Isolation in the ALU
15.35-16.00		COFFEE BREAK
16.00-17.45		Session 5.1 Architecture Innovation for System Robustness and Performance Session Chair: Sung Woo Chung, Korea University, South Korea			Session 5.2 Modeling and Optimization for Test Development Session Chair: Klaus Schneider, University of Kaiserslautern, Germany			Session 5.3 Energy and Performance Optimization
	PAPER ID	ROOM 1		PAPER ID	ROOM 2		PAPER ID	ROOM 3
16.00	239	Arun K. Kanuparthi, Mohamed Zahran and Ramesh Karri	16.00	67	Andreas Merentitis, Antonis Paschalis, Dimitris Gizopoulos and Nektarios Kranitis	16.00	309	Jeff Pool, Anselmo Lastra and Montek Singh
	REG	Feasibility Study of Dynamic Trusted Platform Module		REG	Energy-Optimal On-Line Self-Test of Microprocessors in WSN Nodes		REG	An Energy Model for Graphics Processing Units
16.25	39	Nicolas Zea, John Sartori, Ben Ahrens and Rakesh Kumar	16.25	19	Zhenyu Qi, Brett Meyer, Wei Huang, Robert Ribando, Kevin Skadron and Mircea Stan	16.25	315	Benedikt Dietrich, Swaroop Nunna, Dip Goswami, Samarjit Chakraborty and Matthias Gries
	REG	Optimal Power/Performance Pipelining for Error Resilient Processors		REG	Temperature-to-Power Mapping		REG	LMS-based Low-Complexity Game Workload Prediction for DVFS
16.50	173	Hans Vandierendonck and Koen De Bosschere	16.50	305	Baris Arslan and Alex Orailoglu	16.50	229	Samuel Antao and Leonel Sousa
	REG	Implicit Hints: Embedding Hint Bits in Programs without ISA Changes		REG	Delay Test Quality Maximization through Process-aware Selection of Test Set Size		REG	Exploiting SIMD Extensions for Linear Image Processing with OpenCL
17.15	51	Dongkyun Ahn and Gyungho Lee	17.15	37	Ahmad Patooghy, Seyed Ghassem Miremdai and Mansour Shafaei	17.15	257	Jason Loew, Jesse Elwell, Dmitry Ponomarev and Patrick Madden
	SHORT	Countering code injection attacks with TLB and I/O monitoring		SHORT	Crosstalk Modeling to Predict Channel Delay in Network-on-Chips		REG	A Co-Processor Approach for Accelerating Data-Structure Intensive Algorithms
			17.30	64	Yeonbok Lee, Takeshi Matsumoto and Masahiro Fujita
				SHORT	Generation of I/O Sequences for A High-level Design from Those in Post-Silicon for Efficient Post-Silicon Debugging
18.00-19.30		BOAT TOUR (starting from the Conference hotel)
		Wednesday October 6, 2010
08.00-08.30		WELCOME COFFEE
08.30-10.10		Session 6.1 Network-on-Chips Session Chair: Ben Juurlink, Technical Univ. of Berlin, Germany			Session 6.2 Verification and Design for Test with Reduced Overhead Session Chair: Alex Orailoglu, University of California San Diego, USA
	PAPER ID	ROOM 1		PAPER ID	ROOM 2
08.30	70	Tushar Krishna, Jacob Postman, Christopher Edmonds, Li-Shiuan Peh and Patrick Chiang	08.30	62	Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli and Nicola Orlandi
	REG	SWIFT: A SWing-reduced Interconnect For a Token-based Network-on-Chip in 90nm CMOS		REG	DDPSL: an Easy Way of Defining Properties
08.55	15	Arseniy Vitkovskiy, Vassos Soteriou and Chrysostomos Nicopoulos	08.55	33	Jia Li and Dong Xiang
	REG	A Fine-Grained Link-Level Fault Tolerant Mechanism for NoCs		REG	DfT Optimization for Pre-Bond Testing of 3D-SICs containing TSVs
09.20	299	Junbok You, Daniel Gebhardt and Kenneth Stevens	09.20	179	Thomas Indlekofer, Michael Schnittger and Sybille Hellebrand
	REG	Bandwidth Optimization in Asynchronous NoCs by Customizing Link Wire Length		REG	Efficient Test Response Compaction for Robust BIST using Parity Sequences
09.45	120	Qi Shubo, Zhang Minxuan, Li Jinwen, Zhao Tianlei, Zhang Chengyi and Li Shaoqing	09.45	203	Debapriya Chatterjee and Valeria Bertacco
	SHORT	A High Performance Router With Dynamic Buffer Allocation For On-Chip Interconnect Networks		REG	EQUIPE: Parallel Equivalence Checking with GP-GPUs
10.10-10.45		COFFEE BREAK
10.45-12.10		Session 7.1 Energy Efficient Architecture Session Chair: Andrei Terechko, Vector Fabrics, The Netherlands			Session 7.2 Power and Thermal Analysis and Optimization Session Chair: Baris Taskin, Drexel University, USA
	PAPER ID	ROOM 1		PAPER ID	ROOM 2
10.45	61	Christos Strydis and Dhara Dave	10.45	184	Shervin Sharifi and Tajana Rosing
	SHORT	Identifying optimal biomedical implant-processor designs		REG	Package-Aware Scheduling of Embedded Workloads for Temperature and Energy Management on Heterogeneous MPSoCs
11.00	63	Hyung Beom Jang, Jinhang Choi, Ikroh Yoon, Sung-Soo Lim, Seungwon Shin, Naehyuck Chang and Sung Woo Chung
			11.10	44	Yu Liu and Kaijie Wu
	SHORT	Exploiting Application-dependent Ambient Temperature for Accurate Architectural Simulation		SHORT	Towards cool and reliable digital systems: RT level CED techniques with runtime adaptability
11.15	154	Subhra Mazumdar, Dean Tullsen and Justin Song
			11.25	155	Michel Rogers-Vallee, Marc-Andre Cantin, Guy Bois and Laurent Moss
	REG	Inter-socket Victim Cacheing for Platform Power Reduction		SHORT	IP Characterization Methodology for Fast and Accurate Power Consumption Estimation at Transactional Level Model
11.40	139	Meltem Ozsoy, Yusuf Onur Kocberber, Mehmet Kayaalp and Oguz Ergin	11.40	325	Junjun Gu, Lin Yuan and Gang Qu
	REG	Dynamic Register File Partitioning in Superscalar Microprocessors for Energy Efficiency		SHORT	Enhancing Dual-Vt Design by Considering On-Chip Temperature Variation
			11.55	289	Quang Dinh, Deming Chen and Martin Wong
				SHORT	BDD-Based Circuit Restructuring for Reducing Dynamic Power
12.10-12.30		CLOSING by Georgi Gaydadjiev and Peter-Micheal Seidel